1. Field of the Invention
The present invention relates to a semiconductor device having an insulated gate type transistor and an insulated gate type capacitance and a method of manufacturing the semiconductor device.
2. Description of the Background Art
In a transistor having a gate length of a subquarter micron or less, a pocket injecting process for forming a pocket region is executed in order to suppress a short channel effect. The pocket injection is also referred to as NUDC (Non Uniformly Doped Channel).
FIG. 52 is a sectional view showing the pocket injecting process. As shown in FIG. 52, in the formation of a CMOS transistor, an NMOS formation region A11 and a PMOS formation region A12 are isolated from each other through an isolating film 102 provided in an upper layer portion of a semiconductor substrate 101.
In the NMOS formation region A11, a gate oxide film 112 and a gate electrode 113 are formed on a surface of a P well region 111 and a P-type impurity ion 103 is implanted and diffused by using the gate electrode 113 as a mask. Consequently, a P-type impurity implantation region 119 to be a pocket region of an NMOS transistor is formed.
In the PMOS formation region A12, similarly, a gate oxide film 122 and a gate electrode 123 are formed on a surface of an N well region 121 and an N-type impurity ion 104 is implanted and diffused by using the gate electrode 123 as a mask. Consequently, an N-type impurity implantation region 129 to be a pocket region of a PMOS transistor is formed.
More specifically, in the pocket injecting process, an impurity of the same conductivity type as that of a channel region of each MOS transistor is implanted into each of the NMOS formation region A11 and the PMOS formation region A12. In the pocket injecting process, the distribution of an impurity in a direction of a channel length becomes nonuniform and an effective channel impurity concentration is increased when a gate length becomes smaller. As a result, it is possible to suppress the short channel effect.
FIG. 53 is a sectional view showing a state in which a CMOS transistor is finished after the pocket injecting process.
As shown in FIG. 53, in the NMOS formation region A11, N+ source-drain regions 114 and 114 are formed to interpose therebetween a channel region provided under the gate electrode 113 and tip regions opposed to each other between the N+ source-drain regions 114 and 114 are extension portions 114e, respectively.
In a vicinal region of the extension portion 114e, the P-type impurity implantation region 119 remains as a P− pocket region 117 from the extension portion 114e to a part of the channel region. Moreover, side walls 116 and 116 are formed on both side surfaces of the gate electrode 113, respectively.
Thus, an NMOS transistor Q11 is formed by the gate oxide film 112, the gate electrode 113, the N+ source-drain region 114, the side wall 116 and the P− pocket region 117.
In the PMOS formation region A12, P+ source-drain regions 124 and 124 are formed to interpose therebetween a channel region provided under the gate electrode 123 and tip regions opposed to each other between the P+ source-drain regions 124 and 124 are extension portions 124e, respectively.
In a vicinal region of the extension portion 124e, the N-type impurity implantation region 129 remains as an N− pocket region 127 from the extension portion 124e to a part of the channel region. Moreover, side walls 126 and 126 are formed on both side surfaces of the gate electrode 123, respectively.
Thus, a PMOS transistor Q12 is formed by the gate oxide film 122, the gate electrode 123, the P+ source-drain region 124, the side wall 126 and the N− pocket region 127.
On the other hand, in a high-frequency analog circuit or a high-speed digital circuit, it is necessary to manufacture an LC type VCO (Voltage Controlled Oscillator) by using an inductor (L) and a variable capacitance (C).
In the case in which the variable capacitance to be an insulated gate type capacitance which has a small loss is to be obtained by utilizing the structure of the MOS transistor, it is necessary to generate an accumulation type variable capacitance in which impurities in a substrate (a body region) and a fetch electrode portion have the same conductivity type.
FIG. 54 is a sectional view showing a structure of the accumulation type variable capacitance. As shown in FIG. 54, in the formation of the accumulation type variable capacitance, a P-type variable capacitance formation region A13 and an N-type variable capacitance formation region A14 are isolated from each other through an isolating film 102 provided in an upper layer portion of a semiconductor substrate 101.
In the P-type variable capacitance formation region A13, P+ fetch electrode regions 134 and 134 are formed to interpose therebetween a channel region provided under a gate electrode 133 and tip regions opposed to each other between the P+ fetch electrode regions 134 and 134 are extension portions 134e, respectively.
In a vicinal region of the extension portion 134e, an N− pocket region 137 is formed from the extension portion 134e to a part of the channel region. Moreover, side walls 136 and 136 are formed on both side surfaces of the gate electrode 133, respectively.
Thus, a P-type variable capacitance C11 is formed by a gate oxide film 132, the gate electrode 133, the P+ fetch electrode region 134, the side wall 136 and the N− pocket region 137. In other words, the P-type variable capacitance C11 acts as an insulated gate type capacitance in which the P+ fetch electrode region 134 is set to one of electrodes, the gate electrode 133 is set to the other electrode and the gate oxide film 132 is set to an interelectrode insulating film.
In the N-type variable capacitance formation region A14, N+ fetch electrode regions 144 and 144 are formed to interpose therebetween a channel region provided under a gate electrode 143 and tip regions opposed to each other between the N+ fetch electrode regions 144 and 144 are extension portions 144e, respectively.
In a vicinal region of the extension portion 144e, a P− pocket region 147 is formed from the extension portion 144e to a part of the channel region. Moreover, side walls 146 and 146 are formed on both side surfaces of the gate electrode 143, respectively.
Thus, an N-type variable capacitance C12 is formed by a gate oxide film 142, the gate electrode 143, the N+ fetch electrode region 144, the side wall 146 and the P− pocket region 147. In other words, the N-type variable capacitance C12 acts as an insulated gate type capacitance in which the N+ fetch electrode region 144 is set to one of electrodes, the gate electrode 143 is set to the other electrode and the gate oxide film 142 is set to an interelectrode insulating film.
FIGS. 55 and 56 are views illustrating a degree of a change in a capacitance value of the N-type variable capacitance C12. In the case in which a gate voltage VG to be applied to the gate electrode 143 is lower than 0 V, a depletion layer 148 is extended downward in an N well region 121 provided under the gate electrode 143 as shown in FIG. 55 so that a capacitance value of the N-type variable capacitance C12 is decreased. On the other hand, in the case in which the gate voltage VG is higher than 0 V, the depletion layer 148 is reduced in the N well region 121 provided under the gate electrode 143 as shown in FIG. 56 so that the capacitance value of the N-type variable capacitance C12 is increased. Thus, it is possible to variably set the capacitance value of the N-type variable capacitance C12 based on the gate voltage VG to be applied to the gate electrode 143. Also in the P-type variable capacitance C11, similarly, it is possible to change the capacitance value based on the gate voltage to be applied to the gate electrode 133.
However, when the pocket injecting process shown in FIG. 52 is executed in order to enhance a short channel characteristic (to suppress the short channel effect), a pocket region of a reverse conductivity type to that of the body region is formed with the accumulation type variable capacitance in a fetch electrode region and the body region to be a region of the semiconductor substrate 101 which is provided just below the gate electrode. Therefore, there has been a problem in that a series resistance is increased.
FIG. 57 is a circuit diagram showing an equivalent circuit of the variable capacitance in FIG. 54. As shown in FIG. 57, the variable capacitance is equivalently represented by a series connection of a capacitance component C10 and a resistance component R10.
On the other hand, an index representing an electrical characteristic of the variable capacitance includes a Q-factor (Q-value). The Q-value is expressed in the following equation (1), wherein Q represents a Q-value, co represents an angular frequency, C represents a capacitance value of the capacitance component C10 and R represents a resistance value of the resistance component R10.
      [          Equation      ⁢                                        ⁢                                      ⁢      1        ]                                Q          =                      1                          ω              ⁢                                                          ⁢              CR                                                            (          1          )                    
When the Q-value is increased, an energy efficiency of the capacitance is enhanced. There has been a problem in that the resistance value R of the resistance component R10 is increased by the presence of the pocket region so that the Q-value is decreased in accordance with the equation (1). In addition, there has been a problem in that an insulated gate type capacitance generally has a small Q-value.